| PART |
Description |
Maker |
| 74F11200 74F112SJ 74F112 74F112PC 74F112SC 74F112S |
From old datasheet system
Dual JK Negative Edge-Triggered Flip-Flop; Package: SOP; No of Pins: 16; Container: Tape & Reel F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| IN74AC112 |
Dual J-K Negative-Edge-Triggered Flip-Flop
|
IK Semiconductor
|
| KS74AHCT112 |
Dual J-K Negative-Edge-Triggered Flip-Flops
|
Samsung
|
| SN74LS73N |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola
|
| SN74LS112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola, Inc
|
| HD74LS107A HD74LS107AFPEL HD74LS107AP |
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| 74HC73 74HC73D 74HC73N 74HC73DB 74HCT73 |
Dual JK flip-flop with reset; negative-edge trigger
|
http://
NXP Semiconductors
|
| 74HC107D-Q100 74HCT107D-Q100 74HC107PW-Q100 |
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors
|
| 74LCX112MTC |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
|
ON Semiconductor
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
